Impact of precisely positioned dopants on the performance of an ultimate silicon nanowire transistor: a full three-dimensional NEGF simulation study

In this paper, we report the first systematic study of quantum transport simulation of the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications. Due to strong inhomogeneity of the selfconsistent electrostatic potential, a full 3-D real-space nonequilibrium Green function formalism is used. The simulations are carried out for an n-channel NWT with 2.2 × 2.2 nm2 cross section and 6-nm channel length, where the locations of the precisely arranged dopants in the source-drain extensions and in the channel region have been varied. The individual dopants act as localized scatters, and hence, impact of the electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the ON-current and a modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices with microscopically different discrete dopant configurations. The variations of the current-voltage characteristics are analyzed with reference to the behavior of the transmission coefficients

Does a Nanowire Transistor Follow the Golden Ratio? A 2D Poisson-Schrödinger/3D Monte Carlo Simulation Study

In this work, we observed the signatures of isotropic charge distributions showing the same attributes as the golden ratio (Phi) described in art and architecture, we also present a simulation study of ultra-scaled n-type silicon nanowire transistors (NWT) for the 5nm CMOS application. Our results reveal that the amount of mobile charge in the channel is determined by the device geometry and could also be related to the golden ratio (Phi). We also established a link between the main device characteristics, such as a drive and leakage current, and cross-sectional shape and dimensions of the device. We discussed the correlation between the main Figure of Merit (FoM) and the device variability and reliability

Position-Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we investigated the performance of vertically stacked lateral nanowires transistors (NWTs) considering the effects of series resistance. Also, we consider the vertical positions of the lateral nanowires in the stack and diameter variation of the lateral NWTs as new sources of process variability

Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work

Variability-Aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs) considering various sources of statistical variability. Our simulation approach is based on various simulations techniques to capture the complexity in such ultra-scaled device

Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study

In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson-Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs

2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application

Traditional memory devices are facing more challenges due to continuous down-scaling. 6T-SRAM suffers from variability [1-2] and reliability [3-4] issues, which introduce cell stability problems. DRAM cells with one transistor, one capacitor (1T1C) struggle to maintain refresh time [5-6]. Efforts have been made to find new memory solutions, such as one transistor (1T) solutions [7-9]. Floating body based memory structures are among the potential candidates, but impact ionization or band-to-band tunnelling (B2BT) limits their refresh time [10]. A recently proposed zero impact ionization and zero subthreshold swing device named Z2FET [9, 11-12] has been demonstrated and is a promising candidate for 1T DRAM memory cell due to technology advantages such as CMOS technology compatibility, novel capacitor-less structure and sharp switching characteristics. In the Z2FET memory operation, refresh frequency is determined by data retention time. Previous research [11-12] is lacking systematic simulation analysis and understanding on the underlying mechanisms. In this paper, we propose a new simulation methodology to accurately extract retention time in Z2FET devices and understand its dependency on applied biases, temperatures and relevant physical mechanisms. Since the stored ‘1’ state in Z2FET is an equilibrium state [9, 11-12] and there is no need to refresh, we will concentrate on state ‘0’ retention. Two types of ‘0’ retention time: HOLD ‘0’ and READ ‘0’ retention time will be discussed separately

Simulation of Gated GaAs-AlGaAs Resonant Tunneling Diodes for Tunable Terahertz Communication Applications

In this work, we report simulations on a GaAs-AlGaAs gated nanowire resonant tunneling diode (RTD) for tunable terahertz communication applications. All calculations are performed with the self-consistent Non-Equilibrium Green’s Function (NEGF) quantum transport formalism implemented in our in-house Nano-Electronic Simulation Software (NESS). Our simulations successfully capture the detailed picture of the quantum mechanical effects such as quantum confinement and resonant tunneling of electrons through barriers in such structures. Moreover, we report for the first time the correlation between the gate-bias voltage and the position of the resonant peak (VR) in the current - voltage characteristics. Such Vr, which is associated with tunneling effects in RTD, could lead to tunable terahertz generation and detection for communication applications

Thorough understanding of retention time of Z2FET memory operation

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD ``0'' retention time originates from the gated-silicon on insulator (SOI) portion rather than the intrinsic-SOI region of the Z2FET. Electrons accumulate under front gate and finally collapse the potential barrier turning logic ``0''-``1.'' It appears that Shockley-Read-Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. The results show that the downscaling of Lg has little effect on data ``0'' retention, but Lin is limited to ~ 125 nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75 nm. We have demonstrated by 2-D TCAD simulation that Z2FET is a promising DRAM cells' candidate particularly for Internet-of-Things applications

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions. ? 2015 IEEE.E